Cloud Computing MCQ Quiz Hub

1. Data hazards occur when .....................
greater performance loss
pipeline changes the order of read/write access to operands
some functional unit is not fully pipelined
machine size is limited

2. Systems that do not have parallel processing capabilities are
sisd
simd
mimd
all of the above

3. How does the number of transistors per chip increase according to Moore ´s law?
quadratically
linearly
cubicly
exponentially

4. Parallel processing may occur
in the instruction stream
in the data stream
both[a] and [b]
None of these

5. Execution of several activities at the same time.
processing
parallel processing
serial processing
multitasking

6. Cache memory works on the principle of
locality of data ??
locality of memory
locality of reference ??
locality of reference & memory

7. SIMD represents an organization that ______________.
?? ?? ?? refers to a computer system capable of processing ???? ?? ?? ?? several programs at the same time.
?? ?? ?? represents organization of single computer containing ?? ?? a control unit, processor unit and a memory unit.
?? ?? ?? includes many processing units under the supervision ?? ?? ?? ?? ?? of a common control unit
None of the above

8. A processor performing fetch or decoding of different instruction during the execution of another instruction is called ______ .
super-scaling
pipe-lining
parallel computation
none of these

9. General MIMD configuration usually called
a multiprocessor
a vector processor
array processor
none of the above.

10. A Von Neumann computer uses which one of the following?
sisd
simd
misd
mimd

11. A Von Neumann computer uses which one of the following?
sisd
simd
misd
mimd

12. MIMD stands for
multiple instruction multiple data
multiple instruction memory data
memory instruction multiple data
multiple information memory data

13. MIPS stands for:
memory instruction per second
major instruction per second
main information per second
million instruction per second

14. M.J. Flynn's parallel processing classification is based on:
multiple instructions
multiple data
both (a) and (b)
none of the above

15. VLIW stands for:
vector large instruction word
very long instruction word
very large integrated word
very low integrated word

16. The major disadvantage of pipeline is:
high cost individual dedicated
initial setup time
if branch instruction is encountered the pipe has to be flushed
All of the above

17. A topology that involves Tokens.
star
ring
bus
daisy chaining

18. multipoint topology is
bus
star
mesh
ring

19. Which mechanism performs an analysis on the code to determine which data items may become unsafe for caching, and they mark those items accordingly?
directory protocol
snoopy protocol
server based cache coherence
compiler based cache coherence

20. How many processors can be organized in 5-dimensional binary hypercube system?
25
10
32
20

21. Multiprocessors are classified as ________.
simd
mimd
sisd
misd

22. Which of the following is not one of the interconnection structures?
crossbar switch
hypercube system
single port memory
time-shared common bus

23. Which combinational device is used in crossbar switch for selecting proper memory from multiple addresses?
multiplexer
decoder
encoder
demultiplexer

24. How many switch points are there in crossbar switch network that connects 9 processors to 6 memory modules?
50
63
60
54

25. In a three-cube structure, node 101 cannot communicate directly with node?
1
11
100
111

26. Which method is used as an alternative way of snooping-based coherence protocol?
directory protocol
memory protocol
compiler based protocol
none of above

27. snoopy cache protocol are used in -----------------based system
bus
mesh
star
hypercube

28. superscalar architecture contains -------------execution units for instruction execution
multiple
single
both (a) and (b)
none of the above

29. time taken by header of a message between two directly connected nodes is called as-----------------
startup time
per hop time
per word transfer time
packaging time

30. the number of switch requirement for a network with n input and n output is ------------------
n
n2
n3
n4

31. which of the following is not static network
bus
ring
mesh
crossbar switch

32. In super-scalar processors, ________ mode of execution is used.
in-order
post order
out of order
none of the mentioned

33. ___ have been developed specifically for pipelined systems.
A. utility software
speed up utilities
optimizing compilers
None of the above

34. Which of the following is a combination of several processors on a single chip?
multicore architecture
risc architecture
cisc architecture
subword parallelism

35. The important feature of the VLIW is .....
ilp
cost effectiveness
performance
none of the mentioned

36. The parallel execution of operations in VLIW is done according to the schedule determined by ..
sk scheduler
interpreter
compiler
encoder

37. The VLIW processors are much simpler as they do not require of .....
computational register
complex logic circuits
ssd slots
scheduling hardware

38. The VLIW architecture follows ..... approach to achieve parallelism.
misd
sisd
simd
mimd

39. Which of the following is not a Pipeline Conflicts?
timing variations
branching
load balancing
data dependency

40. Which of the following statements is NOT TRUE for Internal Sorting algorithms
usually deal with small number of elements
no of elements must be able to fit in processs main memory
use auxilliary memory like tape or hard disk
ususally are of type compare-exchange

41. In sorting networks for INCREASING COMPARATOR with input x,y select the correct output X', Y' from the following options
x = min { x , y } and y = min { x , y }
x = max { x , y } and y = min { x , y }
x = min { x , y } and y = max{ x , y }
x = max { x , y } and y = max { x , y }

42. In sorting networks for DECREASING COMPARATOR with input x,y select the correct output X', Y' from the following options
x = min { x , y } and y = min { x , y }
x = max { x , y } and y = min { x , y }
x = min { x , y } and y = max{ x , y }
x = max { x , y } and y = max { x , y }

43. Which of the following is TRUE for Bitonic Sequence a) Monotonically increasing b) Monotonically Decreasing c) With cyclic shift of indices d) First increasing then decreasing
a) and b)
a) and b) and d)
a) and b) and c)
a) and b) and c) and d)

44. Which of the following is NOT a BITONIC Sequence
{8, 6, 4, 2, 3, 5, 7, 9}
{0, 4, 8, 9, 2, 1}
{3, 5, 7, 9, 8, 6, 4, 2}
{1, 2, 4, 7, 6, 0, 1}

45. The procedure of sorting a bitonic sequence using bitonic splits is called
bitonic merge
bitonic split
bitonic divide
bitonic series

46. While mapping Bitonic sort on Hypercube, Compare-exchange operations take place between wires whose labels differ in
one bit
two bits
three bits
four bits

47. Which of following is NOT A WAY of mapping the input wires of the bitonicsorting network to a MESH of processes
row major mapping
column major mapping
row major snakelike mapping
row major shuffled mapping

48. Which is the sorting algorithm in below given steps - 1. procedure X_SORT(n) 2. begin 3. for i := n - 1 downto 1 do 4. for j := 1 to i do 5. compare-exchange(aj, aj + 1); 6. end X_SORT
selection sort
bubble sort
parallel selcetion sort
parallel bubble sort

49. The odd-even transposition algorithm sorts n elements in n phases (n is even), each of which requires ------------compare-exchange operations
2n
n2
n/2
n

50. What is TRUE about SHELL SORT
moves elements only one position at a time
moves elements long distance
during second phase algorithm switches to odd even transposition sort
both 2 and 3