R4RIN – MCQs, Mock Tests | Cloud Computing High Performance Computing Set 3

Data hazards occur when .....................

1. greater performance loss
2. pipeline changes the order of read/write access to operands
3. some functional unit is not fully pipelined
4. machine size is limited

✅ Correct Answer: 2

Systems that do not have parallel processing capabilities are

1. sisd
2. simd
3. mimd
4. all of the above

✅ Correct Answer: 1

How does the number of transistors per chip increase according to Moore ´s law?

1. quadratically
2. linearly
3. cubicly
4. exponentially

✅ Correct Answer: 4

Parallel processing may occur

1. in the instruction stream
2. in the data stream
3. both[a] and [b]
4. None of these

✅ Correct Answer: 3

Execution of several activities at the same time.

1. processing
2. parallel processing
3. serial processing
4. multitasking

✅ Correct Answer: 2

Cache memory works on the principle of

1. locality of data ??
2. locality of memory
3. locality of reference ??
4. locality of reference & memory

✅ Correct Answer: 3

SIMD represents an organization that ______________.

1. ?? ?? ?? refers to a computer system capable of processing ???? ?? ?? ?? several programs at the same time.
2. ?? ?? ?? represents organization of single computer containing ?? ?? a control unit, processor unit and a memory unit.
3. ?? ?? ?? includes many processing units under the supervision ?? ?? ?? ?? ?? of a common control unit
4. None of the above

✅ Correct Answer: 3

A processor performing fetch or decoding of different instruction during the execution of another instruction is called ______ .

1. super-scaling
2. pipe-lining
3. parallel computation
4. none of these

✅ Correct Answer: 2

General MIMD configuration usually called

1. a multiprocessor
2. a vector processor
3. array processor
4. none of the above.

✅ Correct Answer: 1

A Von Neumann computer uses which one of the following?

1. sisd
2. simd
3. misd
4. mimd

✅ Correct Answer: 1

A Von Neumann computer uses which one of the following?

1. sisd
2. simd
3. misd
4. mimd

✅ Correct Answer: 1

MIMD stands for

1. multiple instruction multiple data
2. multiple instruction memory data
3. memory instruction multiple data
4. multiple information memory data

✅ Correct Answer: 1

MIPS stands for:

1. memory instruction per second
2. major instruction per second
3. main information per second
4. million instruction per second

✅ Correct Answer: 4

M.J. Flynn's parallel processing classification is based on:

1. multiple instructions
2. multiple data
3. both (a) and (b)
4. none of the above

✅ Correct Answer: 3

VLIW stands for:

1. vector large instruction word
2. very long instruction word
3. very large integrated word
4. very low integrated word

✅ Correct Answer: 2

The major disadvantage of pipeline is:

1. high cost individual dedicated
2. initial setup time
3. if branch instruction is encountered the pipe has to be flushed
4. All of the above

✅ Correct Answer: 4

A topology that involves Tokens.

1. star
2. ring
3. bus
4. daisy chaining

✅ Correct Answer: 2

multipoint topology is

1. bus
2. star
3. mesh
4. ring

✅ Correct Answer: 1

Which mechanism performs an analysis on the code to determine which data items may become unsafe for caching, and they mark those items accordingly?

1. directory protocol
2. snoopy protocol
3. server based cache coherence
4. compiler based cache coherence

✅ Correct Answer: 4

How many processors can be organized in 5-dimensional binary hypercube system?

1. 25
2. 10
3. 32
4. 20

✅ Correct Answer: 3

Multiprocessors are classified as ________.

1. simd
2. mimd
3. sisd
4. misd

✅ Correct Answer: 2

Which of the following is not one of the interconnection structures?

1. crossbar switch
2. hypercube system
3. single port memory
4. time-shared common bus

✅ Correct Answer: 3

Which combinational device is used in crossbar switch for selecting proper memory from multiple addresses?

1. multiplexer
2. decoder
3. encoder
4. demultiplexer

✅ Correct Answer: 1

How many switch points are there in crossbar switch network that connects 9 processors to 6 memory modules?

1. 50
2. 63
3. 60
4. 54

✅ Correct Answer: 4

In a three-cube structure, node 101 cannot communicate directly with node?

1. 1
2. 11
3. 100
4. 111

✅ Correct Answer: 2

Which method is used as an alternative way of snooping-based coherence protocol?

1. directory protocol
2. memory protocol
3. compiler based protocol
4. none of above

✅ Correct Answer: 1

snoopy cache protocol are used in -----------------based system

1. bus
2. mesh
3. star
4. hypercube

✅ Correct Answer: 1

superscalar architecture contains -------------execution units for instruction execution

1. multiple
2. single
3. both (a) and (b)
4. none of the above

✅ Correct Answer: 2

time taken by header of a message between two directly connected nodes is called as-----------------

1. startup time
2. per hop time
3. per word transfer time
4. packaging time

✅ Correct Answer: 2

the number of switch requirement for a network with n input and n output is ------------------

1. n
2. n2
3. n3
4. n4

✅ Correct Answer: 2

which of the following is not static network

1. bus
2. ring
3. mesh
4. crossbar switch

✅ Correct Answer: 4

In super-scalar processors, ________ mode of execution is used.

1. in-order
2. post order
3. out of order
4. none of the mentioned

✅ Correct Answer: 3

___ have been developed specifically for pipelined systems.

1. A. utility software
2. speed up utilities
3. optimizing compilers
4. None of the above

✅ Correct Answer: 3

Which of the following is a combination of several processors on a single chip?

1. multicore architecture
2. risc architecture
3. cisc architecture
4. subword parallelism

✅ Correct Answer: 1

The important feature of the VLIW is .....

1. ilp
2. cost effectiveness
3. performance
4. none of the mentioned

✅ Correct Answer: 1

The parallel execution of operations in VLIW is done according to the schedule determined by ..

1. sk scheduler
2. interpreter
3. compiler
4. encoder

✅ Correct Answer: 3

The VLIW processors are much simpler as they do not require of .....

1. computational register
2. complex logic circuits
3. ssd slots
4. scheduling hardware

✅ Correct Answer: 4

The VLIW architecture follows ..... approach to achieve parallelism.

1. misd
2. sisd
3. simd
4. mimd

✅ Correct Answer: 4

Which of the following is not a Pipeline Conflicts?

1. timing variations
2. branching
3. load balancing
4. data dependency

✅ Correct Answer: 3

Which of the following statements is NOT TRUE for Internal Sorting algorithms

1. usually deal with small number of elements
2. no of elements must be able to fit in processs main memory
3. use auxilliary memory like tape or hard disk
4. ususally are of type compare-exchange

✅ Correct Answer: 3

In sorting networks for INCREASING COMPARATOR with input x,y select the correct output X', Y' from the following options

1. x = min { x , y } and y = min { x , y }
2. x = max { x , y } and y = min { x , y }
3. x = min { x , y } and y = max{ x , y }
4. x = max { x , y } and y = max { x , y }

✅ Correct Answer: 3

In sorting networks for DECREASING COMPARATOR with input x,y select the correct output X', Y' from the following options

1. x = min { x , y } and y = min { x , y }
2. x = max { x , y } and y = min { x , y }
3. x = min { x , y } and y = max{ x , y }
4. x = max { x , y } and y = max { x , y }

✅ Correct Answer: 2

Which of the following is TRUE for Bitonic Sequence a) Monotonically increasing b) Monotonically Decreasing c) With cyclic shift of indices d) First increasing then decreasing

1. a) and b)
2. a) and b) and d)
3. a) and b) and c)
4. a) and b) and c) and d)

✅ Correct Answer: 4

Which of the following is NOT a BITONIC Sequence

1. {8, 6, 4, 2, 3, 5, 7, 9}
2. {0, 4, 8, 9, 2, 1}
3. {3, 5, 7, 9, 8, 6, 4, 2}
4. {1, 2, 4, 7, 6, 0, 1}

✅ Correct Answer: 4

The procedure of sorting a bitonic sequence using bitonic splits is called

1. bitonic merge
2. bitonic split
3. bitonic divide
4. bitonic series

✅ Correct Answer: 1

While mapping Bitonic sort on Hypercube, Compare-exchange operations take place between wires whose labels differ in

1. one bit
2. two bits
3. three bits
4. four bits

✅ Correct Answer: 1

Which of following is NOT A WAY of mapping the input wires of the bitonicsorting network to a MESH of processes

1. row major mapping
2. column major mapping
3. row major snakelike mapping
4. row major shuffled mapping

✅ Correct Answer: 2

Which is the sorting algorithm in below given steps - 1. procedure X_SORT(n) 2. begin 3. for i := n - 1 downto 1 do 4. for j := 1 to i do 5. compare-exchange(aj, aj + 1); 6. end X_SORT

1. selection sort
2. bubble sort
3. parallel selcetion sort
4. parallel bubble sort

✅ Correct Answer: 1

The odd-even transposition algorithm sorts n elements in n phases (n is even), each of which requires ------------compare-exchange operations

1. 2n
2. n2
3. n/2
4. n

✅ Correct Answer: 3

What is TRUE about SHELL SORT

1. moves elements only one position at a time
2. moves elements long distance
3. during second phase algorithm switches to odd even transposition sort
4. both 2 and 3

✅ Correct Answer: 4